CLK_IN_D_0 rst_n_0 util_ds_buf_0 Utility Buffer CLK_IN_D IBUF_OUT[0:0] xlconstant_0 Constant dout[0:0] DataSource_Scrambler_0 DataSource_Scrambler_v1_0 clk reset_n clk_enable ce_out simStart simEnd simEN ScramblerOut[7:0] BinEn DataGenEn TSout[7:0] RS_Enc_0 RS_Enc_v1_0 clk reset_n clk_enable Trigger RS_In[7:0] RS_Start RS_End RS_VLD ce_out RS_Out[7:0] Interleaver_0 Interleaver_v1_0 clk reset_n clk_enable Trigger DataIn[7:0] ce_out InterOut[7:0] dec2bin_0 dec2bin_v1_0 clk reset_n clk_enable DEC_IN[7:0] BinGen ce_out BIN_OUT Con_Encoder_0 Con_Encoder_v1_0 clk reset_n clk_enable In1 VldIn ce_out ConvOut_0 ConvOut_1 PolarityShift_0 PolarityShift_v1_0 m_axis_data clk rst_n bin_ena singleIn PolarityShift_1 PolarityShift_v1_0 m_axis_data clk rst_n bin_ena singleIn dds_compiler_0 DDS Compiler M_AXIS_DATA m_axis_data_tdata[15:0] aclk fir_compiler_0 FIR Compiler S_AXIS_DATA M_AXIS_DATA m_axis_data_tdata[23:0] aclk dds_compiler_1 DDS Compiler M_AXIS_DATA m_axis_data_tdata[15:0] aclk fir_compiler_1 FIR Compiler S_AXIS_DATA M_AXIS_DATA m_axis_data_tdata[23:0] aclk mult_gen_0 Multiplier CLK A[15:0] B[23:0] P[40:0] mult_gen_1 Multiplier CLK A[15:0] B[23:0] P[40:0] c_addsub_0 Adder/Subtracter A[40:0] B[40:0] CLK S[41:0] terminal_0 terminal_v1_0 clk IN_port[41:0] OUT_port OUT_port_0